Filtered by: Simulation × Clear all

Microflow: Microarchitectural Causal Observability for Deep Cross-Layer Analysis and Optimization

Saber Ganjisaffar, Chengyu Song, Nael Abu-Ghazaleh 2026-07-18
Microarchitectural Microarchitecture Simulation ×

The problem is that existing architectural simulators expose only aggregate metrics or raw traces, failing to reveal complex interactions among microarchitectural events and their relationship to program execution. Microflow introduces an observability framework that elevates causality to a first-class analytical object by transforming execution traces into the Microflow Intermediate Representation (MFIR), which explicitly captures dependencies across software semantics, instructions, microarchitectural events, and hardware resources. Experimental evidence from two SPEC CPU 2017 benchmarks demonstrates that Microflow precisely attributes stalls, reveals unobservable phenomena, and enables exact critical-path decomposition, uncovering hidden misprediction costs in leela and cross-loop-iteration contention in mcf. This matters because making causality queryable provides a strong foundation for systematic performance analysis and hardware-software co-design, enabling architects to reason about complex interactions opaque to existing tools.

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ExaGEMM: Exploration Framework for CPU-Driven ML Inference via Associative In-Register Computing for Low-Bit GEMM

Hyunwoo Oh, Suyeon Jang, Hanning Chen, Sanggeon Yun 2026-07-18
Gem5 Microarchitecture Simulation × Inference

The problem is that low-bit GEMM is central to efficient ML inference, but very-low-bit execution is poorly suited for conventional CPUs, and fragmented precision regimes make lightweight CPU support selection a first-class design challenge. ExaGEMM proposes a workload-aware codesign framework for CPU-native low-bit GEMM using register-resident LUT execution, requiring only an in-register select/feed mechanism as new hardware. Experimental results show that ExaGEMM improves latency by 13.29x over software-only baselines across representative ML models and CPU targets, with workload-aware frontier selection being especially important for mixed-precision LLM workloads. This matters because it enables efficient CPU-driven ML inference for low-bit GEMM without major hardware redesign, addressing a critical gap in practical deployment.

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Valinor: Architectural Support for Fast, Energy-Efficient and Programmable Physical Memory Allocation

Konstantinos Kanellopoulos, Spiros Galanopoulos, Konstantinos Sgouras, Vlad-Petru Nitu 2026-07-18
Workload Runtime Hardware Simulation ×

The problem is that physical memory allocation in current systems incurs high overhead from minor page faults, costing tens of thousands of cycles and accounting for up to 54% of runtime and 40% of energy in short-lived workloads. Valinor introduces a hardware-OS cooperative substrate with a programmable hardware allocation engine that executes compact OS-supplied allocation libraries at near fixed-hardware speed. On a BOOM RISC-V soft core running Linux, Valinor accelerates allocation by 17x, improves end-to-end performance by 16%, and reduces energy by up to 8%, with full-system simulation confirming hardware-class performance across six allocation libraries. This matters because Valinor delivers hardware-class performance without sacrificing programmability, enabling diverse allocation policies and adaptation to new hardware conditions.

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HybridQC: Hardware-Grounded Simulation of Tightly Integrated Hybrid Quantum-Classical Systems

Panayiotis Christou, Shuwen Kan, Ying Mao 2026-07-18
Quant Ph Hardware Simulation × Communication Scheduling Runtime Workload

HybridQC addresses the problem that hybrid quantum-classical system performance is increasingly limited by classical control and communication, not quantum execution, and existing tools ignore system-topology issues like controller bottlenecks. The method introduces a topology-aware discrete-event simulator that models hybrid compute units as configurable graphs of classical and quantum devices, decomposing jobs into typed directed acyclic graphs executed under interchangeable scheduling policies. Experimental evidence shows the simulator achieves mean absolute percentage errors of 3.92%-8.04% for D-Wave QPU access time and 5.26%-19.01% for IBM quantum-seconds, and reveals that balanced 10x HCU scaling improves makespan by only 2.19x-3.42x while scheduling shifts makespan by up to 1.80x. This matters because HybridQC provides a systematic framework to evaluate topology, scheduling, and scaling limits of hybrid architectures before physical deployment, enabling researchers to identify bottlenecks and optimize resource contention.

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