ArchSim: Computer Architecture Simulation as a Service

Sabila Al Jannat, Wenhan Lyu, Le Khanh Trinh Mai, Huizhi Zhao 2026-07-16
Computer Architecture Agentic Microarchitecture Simulation

ArchSim addresses the problem that computer architecture simulation studies are difficult to scale and reproduce due to implicit encoding of configuration, execution, and analysis in scripts. The method introduces declarative hardware topology graphs that auto-generate simulation code, stateless runners for job orchestration, and structured artifact storage for systematic result exploration. Experimental evidence from a 96-configuration GPU simulation matrix shows a median kernel time error of 0.18% relative to hand-written MGPUSim configurations across 95.8% of configurations, with only 1.6 seconds of overhead per simulation. This matters because ArchSim enables scalable, reproducible, and automated simulation studies without custom tooling, significantly lowering the barrier for comprehensive architecture exploration.

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CLIP-3D: Closed-Loop Evaluation of Performance and Physical Constraints for 3D ICs

Shuo Ren, Libo Shen, Yaohui Han, Leilei Jin 2026-07-16
Gem5 Microarchitecture Simulation

CLIP-3D addresses the problem that early-stage 3D-IC architectural exploration using simulators like gem5 fails to account for layout-driven thermal, wire, and cache effects that determine actual throughput. The method introduces a shift-left flow that lifts architectural configurations into a physical block representation via McPAT, CACTI, and HotSpot, then co-optimizes cross-tier macro assignment and in-plane placement using an analytical 3D thermal-aware floorplanner. The abstract does not disclose experimental results. This matters because it enables early-stage design selection based on realized BIPS rather than surrogate metrics, preventing throttling on silicon before sign-off.

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Full-Pipeline Inference Optimization for MiMo-V2.5 Series: Pushing Hybrid SWA Efficiency to the Limit

Xiaomi MiMo Team, Anqi Liu, Aoxin Ma, Bo Chen 2026-07-16
Attention Inference LLM GPU Rdma Serving

The problem is that Hybrid Sliding Window Attention (SWA) reduces compute and KVCache storage compared to Full Attention, but realizing these gains in production requires substantial engineering effort. The method systematically optimizes the KVCache system with layerwise prefetch, SWA-aware prefix cache trees, and specialized placement strategies, and builds GCache, a high-performance distributed cache infrastructure with RDMA-optimized networking. Experimental evidence shows strict O(W) SWA storage and high cache hit rates are achieved, with the system being the first large-scale LLM serving system in production to efficiently cover the Hybrid SWA + MoE + multimodal composite architecture. This matters because it pushes hybrid SWA efficiency to the limit, enabling practical deployment of complex multimodal models with reduced computation and storage overhead.

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Microflow: Microarchitectural Causal Observability for Deep Cross-Layer Analysis and Optimization

Saber Ganjisaffar, Chengyu Song, Nael Abu-Ghazaleh 2026-07-16
Microarchitectural Microarchitecture Simulation

The problem is that existing architectural simulators expose aggregate metrics or raw traces but fail to reveal complex interactions among microarchitectural events and their relationship to program execution. Microflow introduces an observability framework that elevates causality to a first-class analytical object by transforming execution traces into the Microflow Intermediate Representation (MFIR), which explicitly captures dependencies across software semantics, instructions, microarchitectural events, and hardware resources. Experimental evidence on two SPEC CPU 2017 benchmarks demonstrates that Microflow precisely attributes stalls, reveals unobservable phenomena, and enables exact critical-path decomposition, uncovering hidden misprediction costs in leela and cross-loop-iteration contention in mcf. This matters because making causality queryable provides a strong foundation for systematic performance analysis and hardware-software co-design, enabling architects to attribute performance symptoms to root causes across abstraction layers.

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HeteroMosaic: Exposing and Exploiting Heterogeneous Execution Opportunities for Energy-Efficient Edge LLM Inference

Gregory Hyegang Jun, Wesley Pang, Eddie Richter, Mehdi Saeedi 2026-07-16
Roofline HPC Compiler Runtime LLM Inference

HeteroMosaic addresses the problem that existing LLM runtimes underutilize heterogeneous resources in edge SoCs by making coarse device-level decisions or optimizing operators in isolation. The method introduces a heterogeneity-first scheduling framework that uses a heterogeneous roofline model, dependency-preserving micro-batches, and trace-guided co-optimization of scheduling and device allocation. On a balanced AMD Ryzen AI platform, HeteroMosaic achieves up to 1.73X speedup over an iGPU baseline, 1.78X over an NPU baseline, and 2.05X over frameworks like llama.cpp, while reducing energy by up to 45.3%. This matters because it demonstrates significant performance and energy efficiency gains for edge LLM inference by effectively exposing and exploiting cross-accelerator execution opportunities on unified-memory platforms.

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Think Through a Bottleneck: Hourglass Reasoning for Rigorous Induction

Huan Zhu 2026-07-16
Language Model LLM Hardware

The problem is that self-refinement fails to improve few-shot inductive reasoning in large language models because simply prompting explicit rule verbalization is ineffective. The method introduces Hourglass reasoning, which enforces strict context isolation between stages, using a frozen LLM as a meta-constructor to pass only a compressed symbolic state (schema φ and rule T) across stage boundaries. Experimental evidence shows Hourglass raises ARC-AGI-2 best-of-5 accuracy by up to 14 points, nearly doubles GPT-5.5 Verilog synthesis accuracy on ChipBench from 31% to 58%, and reverses the harmful effect of explicit verbalization on BBEH-Linguini with Gemini 3.1 Pro. This matters because it demonstrates that the structural flow of information through isolated reasoning stages, not the language used, drives rigorous inductive reasoning in frozen LLMs.

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Can LLMs Perform Deep Technical Comprehension of Computer Architecture Papers?

Nishant Aggarwal, Ayushi Dubal, Sreeraj Kannakarankodi, Ian McDougall 2026-07-16
Computer Architecture Agentic Microarchitecture Simulation LLM

The problem is that existing LLM evaluations focus on summarization rather than deep technical comprehension, which requires structured critique identifying core mechanisms, buried assumptions, and cross-paper contributions. The method introduces Gauntlet, an open-source pipeline using five independent expert-persona reviewers and an adversarial synthesis stage to analyze computer architecture papers. On 20 ISCA 2025 and HPCA 2026 papers, evaluators preferred Gauntlet over human analysis in 15 of 20 comparisons, with significant advantage on Critical Rigor and only vanishing on Calibration, while humans won on trust and usefulness rather than depth. This matters because Gauntlet demonstrates that multi-agent LLM pipelines can outperform humans in deep technical critique, and the released analyses, scores, and rubric provide a community resource for advancing automated paper comprehension.

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StreamingQEC: Streaming Quantum Error Correction in Tightly Integrated Quantum-Classical Systems via Certified Recurrence

Panayiotis Christou, Shuwen Kan, Hao Wang, Ying Mao 2026-07-16
Design Space Exploration Quant Ph Agentic Architecture

StreamingQEC addresses the problem of modeling resource contention in hybrid quantum-classical systems during fault-tolerant quantum error correction. The method introduces a system-level simulator with explicit discrete-event simulation, an automatic staged-fluid mode for faster exploration, and a certified recurrence mechanism that compresses repeated scheduling states. Experimental evidence shows recurrence achieves a 24.0x host-side speedup while preserving 59,743,936 decoding events for a 16-job anchor workload, and the staged-fluid mode yields a mean makespan error of 2.60%. This matters because it enables system architects to evaluate resource-limited pipeline stalls and saturation under microsecond-scale QEC cycles, which is critical for designing scalable fault-tolerant quantum computers.

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Profiling and Scheduling Complex O-RAN Applications Across the 5G Edge and Cloud

Yoonjae Hwang, Bhaskar Krishnamachari 2026-07-16
Scheduling AI Communication Network Simulation Workload

O-DAG addresses the lack of an integrated methodology for profiling and scheduling O-RAN AI/ML pipelines as DAGs across far-edge, near-edge, and cloud resources. The framework combines DagProfiler for task profiling, a three-tier network topology, an extension of the SAGA scheduler, and a MintEDGE-based simulation module. Experimental evaluation of five scheduling algorithms for slice scheduling across 5K–50K UEs shows HEFT achieves the lowest makespan in all configurations, but scheduler rankings are workload-dependent. This matters because O-DAG enables validated, reproducible placement of complex O-RAN applications under realistic 5G constraints, revealing regime-dependent scheduling behavior and model limitations.

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HybridQC: Hardware-Grounded Simulation of Tightly Integrated Hybrid Quantum-Classical Systems

Panayiotis Christou, Shuwen Kan, Ying Mao 2026-07-16
Quant Ph Hardware Simulation Communication Scheduling Runtime Workload

HybridQC addresses the problem that hybrid quantum-classical system performance is increasingly limited by classical control and communication, not quantum execution, and that existing tools fail to capture system-topology issues like controller bottlenecks and resource contention. The method introduces a topology-aware discrete-event simulator that models hybrid compute units as configurable graphs of classical and quantum devices, decomposes jobs into typed directed acyclic graphs, and supports interchangeable scheduling policies. Calibrated against live D-Wave and IBM processors, HybridQC achieves mean absolute percentage errors of 3.92%-8.04% for D-Wave QPU access time and 5.26%-19.01% for IBM quantum-seconds, and workload experiments show that balanced 10x HCU scaling improves makespan by only 2.19x-3.42x while scheduling policy changes shift makespan by up to 1.80x. This matters because HybridQC provides a systematic framework to evaluate topology, scheduling, and scaling limits of hybrid architectures before physical deployment, enabling researchers to identify bottlenecks and optimize resource allocation.

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