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Valinor: Architectural Support for Fast, Energy-Efficient and Programmable Physical Memory Allocation

Konstantinos Kanellopoulos, Spiros Galanopoulos, Konstantinos Sgouras, Vlad-Petru Nitu 2026-07-18
Workload × Runtime Hardware Simulation

The problem is that physical memory allocation in current systems incurs high overhead from minor page faults, costing tens of thousands of cycles and accounting for up to 54% of runtime and 40% of energy in short-lived workloads. Valinor introduces a hardware-OS cooperative substrate with a programmable hardware allocation engine that executes compact OS-supplied allocation libraries at near fixed-hardware speed. On a BOOM RISC-V soft core running Linux, Valinor accelerates allocation by 17x, improves end-to-end performance by 16%, and reduces energy by up to 8%, with full-system simulation confirming hardware-class performance across six allocation libraries. This matters because Valinor delivers hardware-class performance without sacrificing programmability, enabling diverse allocation policies and adaptation to new hardware conditions.

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HybridQC: Hardware-Grounded Simulation of Tightly Integrated Hybrid Quantum-Classical Systems

Panayiotis Christou, Shuwen Kan, Ying Mao 2026-07-18
Quant Ph Hardware Simulation Communication Scheduling Runtime Workload ×

HybridQC addresses the problem that hybrid quantum-classical system performance is increasingly limited by classical control and communication, not quantum execution, and existing tools ignore system-topology issues like controller bottlenecks. The method introduces a topology-aware discrete-event simulator that models hybrid compute units as configurable graphs of classical and quantum devices, decomposing jobs into typed directed acyclic graphs executed under interchangeable scheduling policies. Experimental evidence shows the simulator achieves mean absolute percentage errors of 3.92%-8.04% for D-Wave QPU access time and 5.26%-19.01% for IBM quantum-seconds, and reveals that balanced 10x HCU scaling improves makespan by only 2.19x-3.42x while scheduling shifts makespan by up to 1.80x. This matters because HybridQC provides a systematic framework to evaluate topology, scheduling, and scaling limits of hybrid architectures before physical deployment, enabling researchers to identify bottlenecks and optimize resource contention.

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