Filtered by: Architecture × Clear all

ArchSim: Computer Architecture Simulation as a Service

Sabila Al Jannat, Wenhan Lyu, Le Khanh Trinh Mai, Huizhi Zhao 2026-07-16
Computer Architecture × Agentic Microarchitecture Simulation

ArchSim addresses the problem that computer architecture simulation studies are difficult to scale and reproduce due to implicit encoding of configuration, execution, and analysis in scripts. The method introduces declarative hardware topology graphs that auto-generate simulation code, stateless runners for job orchestration, and structured artifact storage for systematic result exploration. Experimental evidence from a 96-configuration GPU simulation matrix shows a median kernel time error of 0.18% relative to hand-written MGPUSim configurations across 95.8% of configurations, with only 1.6 seconds of overhead per simulation. This matters because ArchSim enables scalable, reproducible, and automated simulation studies without custom tooling, significantly lowering the barrier for comprehensive architecture exploration.

PDF

Can LLMs Perform Deep Technical Comprehension of Computer Architecture Papers?

Nishant Aggarwal, Ayushi Dubal, Sreeraj Kannakarankodi, Ian McDougall 2026-07-16
Computer Architecture × Agentic Microarchitecture Simulation LLM

The problem is that existing LLM evaluations focus on summarization rather than deep technical comprehension, which requires structured critique identifying core mechanisms, buried assumptions, and cross-paper contributions. The method introduces Gauntlet, an open-source pipeline using five independent expert-persona reviewers and an adversarial synthesis stage to analyze computer architecture papers. On 20 ISCA 2025 and HPCA 2026 papers, evaluators preferred Gauntlet over human analysis in 15 of 20 comparisons, with significant advantage on Critical Rigor and only vanishing on Calibration, while humans won on trust and usefulness rather than depth. This matters because Gauntlet demonstrates that multi-agent LLM pipelines can outperform humans in deep technical critique, and the released analyses, scores, and rubric provide a community resource for advancing automated paper comprehension.

PDF

StreamingQEC: Streaming Quantum Error Correction in Tightly Integrated Quantum-Classical Systems via Certified Recurrence

Panayiotis Christou, Shuwen Kan, Hao Wang, Ying Mao 2026-07-16
Design Space Exploration Quant Ph Agentic Architecture ×

StreamingQEC addresses the problem of modeling resource contention in hybrid quantum-classical systems during fault-tolerant quantum error correction. The method introduces a system-level simulator with explicit discrete-event simulation, an automatic staged-fluid mode for faster exploration, and a certified recurrence mechanism that compresses repeated scheduling states. Experimental evidence shows recurrence achieves a 24.0x host-side speedup while preserving 59,743,936 decoding events for a 16-job anchor workload, and the staged-fluid mode yields a mean makespan error of 2.60%. This matters because it enables system architects to evaluate resource-limited pipeline stalls and saturation under microsecond-scale QEC cycles, which is critical for designing scalable fault-tolerant quantum computers.

PDF

HybridQC: Hardware-Grounded Simulation of Tightly Integrated Hybrid Quantum-Classical Systems

Panayiotis Christou, Shuwen Kan, Ying Mao 2026-07-16
Quant Ph Hardware Simulation Communication Scheduling Runtime Workload

HybridQC addresses the problem that hybrid quantum-classical system performance is increasingly limited by classical control and communication, not quantum execution, and that existing tools fail to capture system-topology issues like controller bottlenecks and resource contention. The method introduces a topology-aware discrete-event simulator that models hybrid compute units as configurable graphs of classical and quantum devices, decomposes jobs into typed directed acyclic graphs, and supports interchangeable scheduling policies. Calibrated against live D-Wave and IBM processors, HybridQC achieves mean absolute percentage errors of 3.92%-8.04% for D-Wave QPU access time and 5.26%-19.01% for IBM quantum-seconds, and workload experiments show that balanced 10x HCU scaling improves makespan by only 2.19x-3.42x while scheduling policy changes shift makespan by up to 1.80x. This matters because HybridQC provides a systematic framework to evaluate topology, scheduling, and scaling limits of hybrid architectures before physical deployment, enabling researchers to identify bottlenecks and optimize resource allocation.

PDF