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NIFA: Nonlinear IMC enhanced FPGA for efficient ML inference

Jiajun Hu, Ruthwik Reddy Sunketa, Lei Zhao, Archit Gajjar 2026-07-20

The problem is that conventional ReRAM-based IMC blocks in FPGAs only support static-weight VMM, limiting efficiency gains for Transformer models that require nonlinear and dynamic matrix-matrix multiplication (DIMM) operations, while ADCs consume over 70% of IMC block area and power. The method proposes NIFA, a novel FPGA architecture integrating an ADC-free IMC block that replaces ADCs with analog content-addressable memories (ACAMs) to natively perform nonlinear operations, combined with FPGA-aware design-space exploration and an efficient mapping for DIMM. Experimental evidence shows up to 40x and 1.9x higher energy efficiency and 4.1x and 2.5x higher area efficiency on CNN and Transformer-based benchmarks, respectively. This matters because it significantly improves FPGA DL inference efficiency and sustains robust gains on Transformer-based workloads, advancing domain-specialized FPGA design for modern ML models.

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RTL-Sequencer: Towards Scalable RTL Timing Prediction with the Sequence-based Paradigm

Ziyan Guo, Wenji Fang, Wenkai Li, Yuchao Wu 2026-07-20

The problem is that existing graph-based RTL timing prediction methods suffer from limited receptive fields, high complexity, and a lack of signal directionality. RTL-Sequencer introduces a sequence-based paradigm that linearizes logic cones via breadth-first traversal and applies modern linear sequence models with four synergistic techniques. Experimental results show significant improvements over state-of-the-art baselines, demonstrating the method's effectiveness. This matters because it enables more scalable and accurate early-stage timing optimization in design automation.

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