Filtered by: Design × Clear all

GORIO: GPU-Centered Remote I/O for Graph ANNS over NVMe-oF

Gen Zhang, Wenhao Gu 2026-07-07

GORIO addresses the problem that graph-based approximate nearest neighbor search (ANNS) vector indexes often exceed GPU memory, and existing CPU-centered remote I/O over NVMe-oF is poorly matched to GPU graph traversal. The method keeps all query evolution, page-miss generation, and resume decisions on the GPU, using the CPU only as an NVMe-oF transport proxy, with a two-layer design for GPU-direct remote I/O and ANNS-specific scheduling. On a SIFT1M DiskANN-style workload over RDMA NVMe-oF, GORIO achieves 1.31× speedup over the state-of-the-art remote-I/O reference and 3.73× over the direct remote page-cache path. This matters because it provides a concrete GPU-centered remote I/O substrate that significantly accelerates graph ANNS for vector databases and retrieval-augmented generation services.

PDF

SMART: A Machine Learning and Monte Carlo Framework for Rapid Analysis of Stochastic Transistor Aging and Process Variation in Digital Circuits

Arash Esshaghi, Siavash Es'haghi, Gholamreza Shahabadi, Alireza Moradi 2026-07-07

The problem is that traditional reliability analysis for digital circuits under stochastic transistor aging and process variation is computationally prohibitive for large designs. SMART integrates machine learning with Monte Carlo simulation, using Random Forest regression and Bayesian optimization to predict gate delay distributions without costly parameter extraction. Experimental validation on ISCAS85 benchmarks shows a 94.54% reduction in analysis time with only 1.63% average accuracy error. This matters because it enables scalable, high-fidelity reliability analysis for designing resilient digital systems in advanced CMOS nodes.

PDF