Filtered by: Microarchitecture × Simulation × Clear all

Microflow: Microarchitectural Causal Observability for Deep Cross-Layer Analysis and Optimization

Saber Ganjisaffar, Chengyu Song, Nael Abu-Ghazaleh 2026-07-18
Microarchitectural Microarchitecture × Simulation ×

The problem is that existing architectural simulators expose only aggregate metrics or raw traces, failing to reveal complex interactions among microarchitectural events and their relationship to program execution. Microflow introduces an observability framework that elevates causality to a first-class analytical object by transforming execution traces into the Microflow Intermediate Representation (MFIR), which explicitly captures dependencies across software semantics, instructions, microarchitectural events, and hardware resources. Experimental evidence from two SPEC CPU 2017 benchmarks demonstrates that Microflow precisely attributes stalls, reveals unobservable phenomena, and enables exact critical-path decomposition, uncovering hidden misprediction costs in leela and cross-loop-iteration contention in mcf. This matters because making causality queryable provides a strong foundation for systematic performance analysis and hardware-software co-design, enabling architects to reason about complex interactions opaque to existing tools.

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ExaGEMM: Exploration Framework for CPU-Driven ML Inference via Associative In-Register Computing for Low-Bit GEMM

Hyunwoo Oh, Suyeon Jang, Hanning Chen, Sanggeon Yun 2026-07-18
Gem5 Microarchitecture × Simulation × Inference

The problem is that low-bit GEMM is central to efficient ML inference, but very-low-bit execution is poorly suited for conventional CPUs, and fragmented precision regimes make lightweight CPU support selection a first-class design challenge. ExaGEMM proposes a workload-aware codesign framework for CPU-native low-bit GEMM using register-resident LUT execution, requiring only an in-register select/feed mechanism as new hardware. Experimental results show that ExaGEMM improves latency by 13.29x over software-only baselines across representative ML models and CPU targets, with workload-aware frontier selection being especially important for mixed-precision LLM workloads. This matters because it enables efficient CPU-driven ML inference for low-bit GEMM without major hardware redesign, addressing a critical gap in practical deployment.

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