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NIFA: Nonlinear IMC enhanced FPGA for efficient ML inference

Jiajun Hu, Ruthwik Reddy Sunketa, Lei Zhao, Archit Gajjar 2026-07-18
Design Space Exploration × Agentic Architecture Inference

The problem is that conventional ReRAM-based analog in-memory computing (IMC) blocks in FPGAs only support static-weight vector-matrix multiplication, limiting efficiency gains for Transformer models that require frequent nonlinear and dynamic matrix-matrix multiplication (DIMM) operations, while the ADCs within each IMC block consume over 70% of its area and power. The method proposes a novel FPGA architecture integrating an ADC-free IMC block that replaces ADCs with analog content-addressable memories (ACAMs) to natively perform nonlinear operations, along with FPGA-aware design-space exploration and efficient mapping to enable DIMM operations for attention computation. Experimental evidence shows that on CNN and Transformer-based benchmarks, the architecture achieves up to 40x and 1.9x higher energy efficiency and 4.1x and 2.5x higher area efficiency, respectively. This matters because it significantly improves FPGA deep learning inference efficiency, particularly for Transformer-based workloads across long input sequences, advancing domain-specialized FPGA design.

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StreamingQEC: Streaming Quantum Error Correction in Tightly Integrated Quantum-Classical Systems via Certified Recurrence

Panayiotis Christou, Shuwen Kan, Hao Wang, Ying Mao 2026-07-18
Design Space Exploration × Quant Ph Agentic Architecture

StreamingQEC addresses the problem of modeling resource contention in tightly integrated quantum-classical systems during fault-tolerant quantum error correction (QEC). The method introduces a system-level simulator with explicit discrete-event simulation, an automatic staged-fluid mode for faster exploration, and a certified recurrence mechanism that compresses repeated transitions. Experimental evidence shows recurrence achieves a 24.0x host-side speedup while preserving 59,743,936 decoding events for a 16-job anchor workload, and the staged-fluid mode yields a mean makespan error of 2.60%. This matters because it enables system architects to evaluate QEC pipeline resource contention and scaling, revealing transfer-limited resource matching and decoder-driven pipeline stalls under microsecond-scale cycles.

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