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NIFA: Nonlinear IMC enhanced FPGA for efficient ML inference

Jiajun Hu, Ruthwik Reddy Sunketa, Lei Zhao, Archit Gajjar 2026-07-18
Design Space Exploration Agentic Architecture × Inference

The problem is that conventional ReRAM-based analog in-memory computing (IMC) blocks in FPGAs only support static-weight vector-matrix multiplication, limiting efficiency gains for Transformer models that require frequent nonlinear and dynamic matrix-matrix multiplication (DIMM) operations, while the ADCs within each IMC block consume over 70% of its area and power. The method proposes a novel FPGA architecture integrating an ADC-free IMC block that replaces ADCs with analog content-addressable memories (ACAMs) to natively perform nonlinear operations, along with FPGA-aware design-space exploration and efficient mapping to enable DIMM operations for attention computation. Experimental evidence shows that on CNN and Transformer-based benchmarks, the architecture achieves up to 40x and 1.9x higher energy efficiency and 4.1x and 2.5x higher area efficiency, respectively. This matters because it significantly improves FPGA deep learning inference efficiency, particularly for Transformer-based workloads across long input sequences, advancing domain-specialized FPGA design.

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StreamingQEC: Streaming Quantum Error Correction in Tightly Integrated Quantum-Classical Systems via Certified Recurrence

Panayiotis Christou, Shuwen Kan, Hao Wang, Ying Mao 2026-07-18
Design Space Exploration Quant Ph Agentic Architecture ×

StreamingQEC addresses the problem of modeling resource contention in tightly integrated quantum-classical systems during fault-tolerant quantum error correction (QEC). The method introduces a system-level simulator with explicit discrete-event simulation, an automatic staged-fluid mode for faster exploration, and a certified recurrence mechanism that compresses repeated transitions. Experimental evidence shows recurrence achieves a 24.0x host-side speedup while preserving 59,743,936 decoding events for a 16-job anchor workload, and the staged-fluid mode yields a mean makespan error of 2.60%. This matters because it enables system architects to evaluate QEC pipeline resource contention and scaling, revealing transfer-limited resource matching and decoder-driven pipeline stalls under microsecond-scale cycles.

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HybridQC: Hardware-Grounded Simulation of Tightly Integrated Hybrid Quantum-Classical Systems

Panayiotis Christou, Shuwen Kan, Ying Mao 2026-07-18
Quant Ph Hardware Simulation Communication Scheduling Runtime Workload

HybridQC addresses the problem that hybrid quantum-classical system performance is increasingly limited by classical control and communication, not quantum execution, and existing tools ignore system-topology issues like controller bottlenecks. The method introduces a topology-aware discrete-event simulator that models hybrid compute units as configurable graphs of classical and quantum devices, decomposing jobs into typed directed acyclic graphs executed under interchangeable scheduling policies. Experimental evidence shows the simulator achieves mean absolute percentage errors of 3.92%-8.04% for D-Wave QPU access time and 5.26%-19.01% for IBM quantum-seconds, and reveals that balanced 10x HCU scaling improves makespan by only 2.19x-3.42x while scheduling shifts makespan by up to 1.80x. This matters because HybridQC provides a systematic framework to evaluate topology, scheduling, and scaling limits of hybrid architectures before physical deployment, enabling researchers to identify bottlenecks and optimize resource contention.

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Hybrid multi-objective evolutionary algorithms for service placement in the computing continuum: a comparative study with genetic traceability

Sergi Vivo, Carlos Guerrero, Isaac Lera 2026-07-18
Design Search Distributed Architecture ×

This paper addresses the multi-objective service placement problem in computing continuum environments by proposing a collaborative hybrid island-model MOEA. The method systematically applies heterogeneous hybridization across two experimental campaigns, co-evolving state-of-the-art MOEAs like NSGA-II, NSGA-III, and SMS-EMOA with periodic solution exchange. Across 30 independent runs, the hybrid method outperforms most standalone baselines, with statistical tests confirming significant improvements and traceability analysis revealing non-uniform contributions among islands. This matters because it demonstrates that hybrid cooperation yields scalable, interpretable performance gains for distributed edge-fog-cloud architectures, enabling more efficient service placement in the computing continuum.

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Ground-Side Mission Plan Compilation with Policy-as-Code Guardrails for Cloud-Native Satellite Platforms

Hsiu-Chi Tsai, Chia-Tung Chung 2026-07-18
Runtime Architecture × Compiler Design GPU Scheduling Accelerator AI

The problem is that cloud-native satellite runtimes lack an open-source ground-side toolchain to compile mission plans into executable artifacts. The method introduces Satellite Mission Compiler, a four-stage pipeline that parses plans against a Pydantic schema, evaluates them with OPA/Rego policy-as-code guardrails, compiles into a WorkflowIntent IR, and renders Argo Workflow DAGs and Kueue Job manifests with DRA support. Experimental evidence includes golden translation evaluations, argo lint, in-process OPA decision reproduction, and live single-node cluster submission with DRA-backed GPU admission on Kueue v0.17.3 and v0.18.3, plus a unified GPU+CPU quota with scheduler-level accelerator fallback. This matters because it provides the first open-source, defense-in-depth validated pipeline for pre-uplink mission plan compilation, bridging the gap between human-authored plans and cloud-native satellite runtimes.

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