HybridQC: Hardware-Grounded Simulation of Tightly Integrated Hybrid Quantum-Classical Systems

HybridQC addresses the problem that hybrid quantum-classical system performance is increasingly limited by classical control and communication, not quantum execution, and that existing tools fail to capture system-topology issues like controller bottlenecks and resource contention. The method introduces a topology-aware discrete-event simulator that models hybrid compute units as configurable graphs of classical and quantum devices, decomposes jobs into typed directed acyclic graphs, and supports interchangeable scheduling policies. Calibrated against live D-Wave and IBM processors, HybridQC achieves mean absolute percentage errors of 3.92%-8.04% for D-Wave QPU access time and 5.26%-19.01% for IBM quantum-seconds, and workload experiments show that balanced 10x HCU scaling improves makespan by only 2.19x-3.42x while scheduling policy changes shift makespan by up to 1.80x. This matters because HybridQC provides a systematic framework to evaluate topology, scheduling, and scaling limits of hybrid architectures before physical deployment, enabling researchers to identify bottlenecks and optimize resource allocation.