Microflow: Microarchitectural Causal Observability for Deep Cross-Layer Analysis and Optimization

Saber Ganjisaffar, Chengyu Song, Nael Abu-Ghazaleh 2026-07-18
Microarchitectural Microarchitecture Simulation

The problem is that existing architectural simulators expose only aggregate metrics or raw traces, failing to reveal complex interactions among microarchitectural events and their relationship to program execution. Microflow introduces an observability framework that elevates causality to a first-class analytical object by transforming execution traces into the Microflow Intermediate Representation (MFIR), which explicitly captures dependencies across software semantics, instructions, microarchitectural events, and hardware resources. Experimental evidence from two SPEC CPU 2017 benchmarks demonstrates that Microflow precisely attributes stalls, reveals unobservable phenomena, and enables exact critical-path decomposition, uncovering hidden misprediction costs in leela and cross-loop-iteration contention in mcf. This matters because making causality queryable provides a strong foundation for systematic performance analysis and hardware-software co-design, enabling architects to reason about complex interactions opaque to existing tools.

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CODA: Algorithm-Hardware Co-design for Edge Video Diffusion via NMP-Enabled Compute-Cache Operator Disaggregation

Yuanpeng Zhang, YuXuan Wu, Yitong Xiao, Chenhao Xue 2026-07-18
Inference Transformer Hardware Design Cache

The problem is that deploying Video Diffusion Models on edge devices is too slow for practical local inference due to iterative Transformer-based denoising. The method, CODA, uses algorithm-hardware co-design to disaggregate compute and cache operators via a DIMM-side near-memory engine, reorganizing cache activity into coalesced segments and overlapping compute with cache execution. Experimental evidence shows CODA achieves up to 1.80x end-to-end speedup and 1.74x higher energy efficiency while preserving generation quality. This matters because it enables practical, privacy-preserving video generation on memory-constrained edge GPUs by overcoming the communication and serialization bottlenecks of Cross-Timestep Caching.

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Are LLM-Generated GPU Kernels Production-Ready? A Trace-Driven Benchmark and Optimization Agent

Lingyun Yang, Yuxiao Wang, Shenghao Liang, Linfeng Yang 2026-07-18
Inference LLM GPU Hardware Agent

Atrex-Bench addresses the problem that existing GPU kernel benchmarks use synthetic or curated workloads, not production traces. The method samples 30 operators and 440 shapes from full-cluster production inference traces, weighting each by observed GPU time and card-hours. Experimental evidence shows the best vanilla coding agent reaches only ~10% of the hardware roofline on production operators, with much of the pass rate from PyTorch fallbacks. The co-released Atrex-Kernel-Agent (AKA) converts zero-FlyDSL fallbacks into real kernels matching hand-tuned baselines, demonstrating that profile-driven optimization is critical for production readiness.

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ExaGEMM: Exploration Framework for CPU-Driven ML Inference via Associative In-Register Computing for Low-Bit GEMM

Hyunwoo Oh, Suyeon Jang, Hanning Chen, Sanggeon Yun 2026-07-18
Gem5 Microarchitecture Simulation Inference

The problem is that low-bit GEMM is central to efficient ML inference, but very-low-bit execution is poorly suited for conventional CPUs, and fragmented precision regimes make lightweight CPU support selection a first-class design challenge. ExaGEMM proposes a workload-aware codesign framework for CPU-native low-bit GEMM using register-resident LUT execution, requiring only an in-register select/feed mechanism as new hardware. Experimental results show that ExaGEMM improves latency by 13.29x over software-only baselines across representative ML models and CPU targets, with workload-aware frontier selection being especially important for mixed-precision LLM workloads. This matters because it enables efficient CPU-driven ML inference for low-bit GEMM without major hardware redesign, addressing a critical gap in practical deployment.

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NIFA: Nonlinear IMC enhanced FPGA for efficient ML inference

Jiajun Hu, Ruthwik Reddy Sunketa, Lei Zhao, Archit Gajjar 2026-07-18
Design Space Exploration Agentic Architecture Inference

The problem is that conventional ReRAM-based analog in-memory computing (IMC) blocks in FPGAs only support static-weight vector-matrix multiplication, limiting efficiency gains for Transformer models that require frequent nonlinear and dynamic matrix-matrix multiplication (DIMM) operations, while the ADCs within each IMC block consume over 70% of its area and power. The method proposes a novel FPGA architecture integrating an ADC-free IMC block that replaces ADCs with analog content-addressable memories (ACAMs) to natively perform nonlinear operations, along with FPGA-aware design-space exploration and efficient mapping to enable DIMM operations for attention computation. Experimental evidence shows that on CNN and Transformer-based benchmarks, the architecture achieves up to 40x and 1.9x higher energy efficiency and 4.1x and 2.5x higher area efficiency, respectively. This matters because it significantly improves FPGA deep learning inference efficiency, particularly for Transformer-based workloads across long input sequences, advancing domain-specialized FPGA design.

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StreamingQEC: Streaming Quantum Error Correction in Tightly Integrated Quantum-Classical Systems via Certified Recurrence

Panayiotis Christou, Shuwen Kan, Hao Wang, Ying Mao 2026-07-18
Design Space Exploration Quant Ph Agentic Architecture

StreamingQEC addresses the problem of modeling resource contention in tightly integrated quantum-classical systems during fault-tolerant quantum error correction (QEC). The method introduces a system-level simulator with explicit discrete-event simulation, an automatic staged-fluid mode for faster exploration, and a certified recurrence mechanism that compresses repeated transitions. Experimental evidence shows recurrence achieves a 24.0x host-side speedup while preserving 59,743,936 decoding events for a 16-job anchor workload, and the staged-fluid mode yields a mean makespan error of 2.60%. This matters because it enables system architects to evaluate QEC pipeline resource contention and scaling, revealing transfer-limited resource matching and decoder-driven pipeline stalls under microsecond-scale cycles.

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Valinor: Architectural Support for Fast, Energy-Efficient and Programmable Physical Memory Allocation

Konstantinos Kanellopoulos, Spiros Galanopoulos, Konstantinos Sgouras, Vlad-Petru Nitu 2026-07-18
Workload Runtime Hardware Simulation

The problem is that physical memory allocation in current systems incurs high overhead from minor page faults, costing tens of thousands of cycles and accounting for up to 54% of runtime and 40% of energy in short-lived workloads. Valinor introduces a hardware-OS cooperative substrate with a programmable hardware allocation engine that executes compact OS-supplied allocation libraries at near fixed-hardware speed. On a BOOM RISC-V soft core running Linux, Valinor accelerates allocation by 17x, improves end-to-end performance by 16%, and reduces energy by up to 8%, with full-system simulation confirming hardware-class performance across six allocation libraries. This matters because Valinor delivers hardware-class performance without sacrificing programmability, enabling diverse allocation policies and adaptation to new hardware conditions.

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A Fast Quantitative Analyzer for NetKAT

Thomas Lu, Qiancheng Fu, Kevin Batz, Oliver Bøving 2026-07-18
Network Design Data Search

The problem is that network engineers need to reason about quantitative trade-offs like bandwidth, latency, and resilience, which existing tools do not support. The method introduces a fast analyzer using weighted NetKAT (wNetKAT) and a symbolic data structure called weighted symbolic packet programs (wSPPs) to compactly represent and compute quantitative network policies. Experimental evidence shows the Rust implementation is competitive with KATch on Boolean reachability and orders of magnitude faster than McNetKAT and Storm on probabilistic analyses, with a case study on Fat-tree and Jellyfish topologies demonstrating multi-objective design-time analysis. This matters because it provides a practical, parametric framework for fast quantitative reasoning about network properties, enabling engineers to explore design trade-offs at scale.

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HybridQC: Hardware-Grounded Simulation of Tightly Integrated Hybrid Quantum-Classical Systems

Panayiotis Christou, Shuwen Kan, Ying Mao 2026-07-18
Quant Ph Hardware Simulation Communication Scheduling Runtime Workload

HybridQC addresses the problem that hybrid quantum-classical system performance is increasingly limited by classical control and communication, not quantum execution, and existing tools ignore system-topology issues like controller bottlenecks. The method introduces a topology-aware discrete-event simulator that models hybrid compute units as configurable graphs of classical and quantum devices, decomposing jobs into typed directed acyclic graphs executed under interchangeable scheduling policies. Experimental evidence shows the simulator achieves mean absolute percentage errors of 3.92%-8.04% for D-Wave QPU access time and 5.26%-19.01% for IBM quantum-seconds, and reveals that balanced 10x HCU scaling improves makespan by only 2.19x-3.42x while scheduling shifts makespan by up to 1.80x. This matters because HybridQC provides a systematic framework to evaluate topology, scheduling, and scaling limits of hybrid architectures before physical deployment, enabling researchers to identify bottlenecks and optimize resource contention.

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Hybrid multi-objective evolutionary algorithms for service placement in the computing continuum: a comparative study with genetic traceability

Sergi Vivo, Carlos Guerrero, Isaac Lera 2026-07-18
Design Search Distributed Architecture

This paper addresses the multi-objective service placement problem in computing continuum environments by proposing a collaborative hybrid island-model MOEA. The method systematically applies heterogeneous hybridization across two experimental campaigns, co-evolving state-of-the-art MOEAs like NSGA-II, NSGA-III, and SMS-EMOA with periodic solution exchange. Across 30 independent runs, the hybrid method outperforms most standalone baselines, with statistical tests confirming significant improvements and traceability analysis revealing non-uniform contributions among islands. This matters because it demonstrates that hybrid cooperation yields scalable, interpretable performance gains for distributed edge-fog-cloud architectures, enabling more efficient service placement in the computing continuum.

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Ground-Side Mission Plan Compilation with Policy-as-Code Guardrails for Cloud-Native Satellite Platforms

Hsiu-Chi Tsai, Chia-Tung Chung 2026-07-18
Runtime Architecture Compiler Design GPU Scheduling Accelerator AI

The problem is that cloud-native satellite runtimes lack an open-source ground-side toolchain to compile mission plans into executable artifacts. The method introduces Satellite Mission Compiler, a four-stage pipeline that parses plans against a Pydantic schema, evaluates them with OPA/Rego policy-as-code guardrails, compiles into a WorkflowIntent IR, and renders Argo Workflow DAGs and Kueue Job manifests with DRA support. Experimental evidence includes golden translation evaluations, argo lint, in-process OPA decision reproduction, and live single-node cluster submission with DRA-backed GPU admission on Kueue v0.17.3 and v0.18.3, plus a unified GPU+CPU quota with scheduler-level accelerator fallback. This matters because it provides the first open-source, defense-in-depth validated pipeline for pre-uplink mission plan compilation, bridging the gap between human-authored plans and cloud-native satellite runtimes.

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