Filtered by: Simulation × Microarchitecture × Clear all

ArchEval: Measuring AI Agents as Computer Architects

Chenyu Wang, Zishen Wan, Jeffrey Ma, Shvetank Prakash 2026-07-07
Computer Architecture Memory Microarchitecture × Simulation × Agentic AI Agents

ArchEval introduces a benchmark and platform with 20 challenges across CPU cores, memory systems, and accelerators, backed by eight simulators, to evaluate LLM agents on computer architecture design and optimization. The method tests agents under three settings: L1 with full simulator feedback, L2 with simulator source code but no automated workflow, and L3 with no runnable feedback before submission. Experimental evidence shows that with L1 support, all four agents reach or exceed baseline performance, but removing support exposes weaknesses—only GPT-5.5 + Codex remains above baseline in L3 (1.21x geomean, 65% win rate), while the other three fall below baseline. This matters because it frames current agents as useful optimization assistants rather than autonomous architects, identifying needed capabilities like simulator-tool use, calibrated prediction, and pre-feedback judgment.

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TileLens: Efficiently Using Large-Granularity Memory Systems with Transparent Two-Dimensional Memory Layout

Jae Hyung Ju, Euijun Chung, Hritvik Taneja, Anish Saxena 2026-07-07
Memory Microarchitecture × Simulation ×

The problem is that Large-Granularity Memory Systems (LGMS) like High-Bandwidth Flash (HBF) degrade LLM inference performance due to read amplification from a mismatch between 2D compute tiles and 1D memory layout. The method, TileLens, introduces a tile-major 2D memory layout with lightweight software (TileLens-SW for DSLs) and hardware (TileLens-HW for TMA) extensions to align memory granularity with tile boundaries. Experimental evidence from cycle-level simulations of Qwen-3 30B and Llama-3.1 70B shows TileLens reduces geomean slowdown from 1.61-6.49x with conventional layouts to within 1% of an HBM-only baseline on HBF-augmented GPUs. This matters because it enables efficient use of higher-capacity or higher-bandwidth memory systems for LLM inference without performance degradation.

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Performance evaluation of scheduling tasks in many-core systems utilizing processes and threads

Mejgan Dedaj, Argyro Gailla, Theofanis Ioannou, Stamatia Kastrinaki 2026-07-07
Memory Microarchitecture × Simulation × Scheduling

This study evaluates the scalability of process-based and thread-based schedulers for many-core systems using a memory-intensive quick-sort workload on large tensors. The method compares bounded prolific, bounded collective, and three pipe-based producer-consumer schedulers for processes, alongside static, dynamic, guided, chunk-based, chunk-stealing, adaptive chunk, and AIMD adaptive scheduling strategies for threads. Experimental results on a 24-core x86-64 platform show that thread schedulers, particularly dynamic and guided, deliver the highest overall performance, while pipe-based process schedulers demonstrate strong scalability with one-to-one pipes excelling for smaller workloads and many-to-many pipes for larger workloads. This matters because it identifies lightweight thread scheduling as optimal for shared-memory row sorting, while AIMD/adaptive and pipe-based schedulers remain valuable for contention-aware execution and distributed-style heterogeneous workload management.

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