SMART: A Machine Learning and Monte Carlo Framework for Rapid Analysis of Stochastic Transistor Aging and Process Variation in Digital Circuits

The problem is that traditional reliability analysis for digital circuits under stochastic transistor aging and process variation is computationally prohibitive for large designs. SMART integrates machine learning with Monte Carlo simulation, using Random Forest regression and Bayesian optimization to predict gate delay distributions without costly parameter extraction. Experimental validation on ISCAS85 benchmarks shows a 94.54% reduction in analysis time with only 1.63% average accuracy error. This matters because it enables scalable, high-fidelity reliability analysis for designing resilient digital systems in advanced CMOS nodes.