ArchEval: Measuring AI Agents as Computer Architects

Chenyu Wang, Zishen Wan, Jeffrey Ma, Shvetank Prakash 2026-07-07
Computer Architecture Memory Microarchitecture Simulation Agentic AI Agents

ArchEval introduces a benchmark and platform with 20 challenges across CPU cores, memory systems, and accelerators, backed by eight simulators, to evaluate LLM agents on computer architecture design and optimization. The method tests agents under three settings: L1 with full simulator feedback, L2 with simulator source code but no automated workflow, and L3 with no runnable feedback before submission. Experimental evidence shows that with L1 support, all four agents reach or exceed baseline performance, but removing support exposes weaknesses—only GPT-5.5 + Codex remains above baseline in L3 (1.21x geomean, 65% win rate), while the other three fall below baseline. This matters because it frames current agents as useful optimization assistants rather than autonomous architects, identifying needed capabilities like simulator-tool use, calibrated prediction, and pre-feedback judgment.

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Elastic Gang: Per-Token Membership Change for a Hard-Barriered LLM Inference Gang Co-Scheduled with OS Processes

Daeyeon Son 2026-07-07
Inference LLM Scheduling

The problem is that on-device LLM decoding is a hard-barriered CPU-SIMD computation requiring all cores per token, but preemptive scheduling causes deadlock or silent logit corruption. The method introduces the elastic gang in Anima OS, using an ACK-latched epoch protocol with generation-tagged latches and RCU-style membership consent to allow per-token core membership changes without waiting on named cores. Experimental evidence on AMD Zen 5 shows bit-exact inference under per-token membership changes for 135M and 7B models, with 1.75x, 1.52x, and 1.28x general throughput improvements over static 8-core splits at 25%, 50%, and 75% inference duty cycles, and core return costs of 0.22 us. This matters because it enables safe, dynamic core sharing between LLM inference and OS processes, Pareto-dominating static partitions and auto-sizing the gang online to maximize throughput without stranded cores.

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TileLens: Efficiently Using Large-Granularity Memory Systems with Transparent Two-Dimensional Memory Layout

Jae Hyung Ju, Euijun Chung, Hritvik Taneja, Anish Saxena 2026-07-07
Memory Microarchitecture Simulation

The problem is that Large-Granularity Memory Systems (LGMS) like High-Bandwidth Flash (HBF) degrade LLM inference performance due to read amplification from a mismatch between 2D compute tiles and 1D memory layout. The method, TileLens, introduces a tile-major 2D memory layout with lightweight software (TileLens-SW for DSLs) and hardware (TileLens-HW for TMA) extensions to align memory granularity with tile boundaries. Experimental evidence from cycle-level simulations of Qwen-3 30B and Llama-3.1 70B shows TileLens reduces geomean slowdown from 1.61-6.49x with conventional layouts to within 1% of an HBM-only baseline on HBF-augmented GPUs. This matters because it enables efficient use of higher-capacity or higher-bandwidth memory systems for LLM inference without performance degradation.

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ELiTeFormer: An Efficient Transformer for FPGAs

Victor Agostinelli, Nicolas Bohm Agostini, Antonino Tumeo 2026-07-07
Attention Language Model LLM Quantization Transformer Fpga GPU

ELiTeFormer addresses the deployment challenge of Transformer blocks in LLMs by co-designing hybrid linear attention with ultra-low-precision ternary projections specifically for FPGAs. The method introduces a novel processing element micro-architecture that eliminates all multiplications in ternary linear projections using bitmasking, avoiding DSP blocks entirely. Experimental results show 10x model weight compression and 12.8x KV cache compression versus LLaMA 3, with block-level simulations achieving 9.6x speedup for FFN and 4.4x for attention, and end-to-end deployment delivering up to 3.9x lower latency and 3.2x better energy efficiency than an NVIDIA A100 GPU. This matters as it demonstrates the first FPGA realization combining linear attention with ternary quantization, proving algorithm-architecture co-design viability for next-generation LLM acceleration.

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Direct Model State Migration for Elastic Training of Large Language Models

Weijian Liu, Mingzhen Li, Rui Kang, Chen Sun 2026-07-07
Language Model LLM Training GPU

The problem is that elastic training of large language models (LLMs) requires state migration across device sets when hybrid-parallel configurations change, but existing checkpoint-based solutions force all GPUs to stall and incur prohibitive latency from data movement across memory hierarchies. ETC proposes a checkpoint-free state migration framework that exploits state locality to minimize inter-GPU data movement, replacing storage persistence with direct peer-to-peer communication and eliminating node fragmentation through communication coalescing. Integrated with Megatron-LM, ETC reduces migration overhead by 2.33× to 6.37× compared to checkpoint-based solutions across diverse parallel configurations. This matters because ETC unlocks practical elastic training in production environments by enabling efficient migration, allowing LLM training to adapt to dynamic resources in shared clusters.

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Performance evaluation of scheduling tasks in many-core systems utilizing processes and threads

Mejgan Dedaj, Argyro Gailla, Theofanis Ioannou, Stamatia Kastrinaki 2026-07-07
Memory Microarchitecture Simulation Scheduling

This study evaluates the scalability of process-based and thread-based schedulers for many-core systems using a memory-intensive quick-sort workload on large tensors. The method compares bounded prolific, bounded collective, and three pipe-based producer-consumer schedulers for processes, alongside static, dynamic, guided, chunk-based, chunk-stealing, adaptive chunk, and AIMD adaptive scheduling strategies for threads. Experimental results on a 24-core x86-64 platform show that thread schedulers, particularly dynamic and guided, deliver the highest overall performance, while pipe-based process schedulers demonstrate strong scalability with one-to-one pipes excelling for smaller workloads and many-to-many pipes for larger workloads. This matters because it identifies lightweight thread scheduling as optimal for shared-memory row sorting, while AIMD/adaptive and pipe-based schedulers remain valuable for contention-aware execution and distributed-style heterogeneous workload management.

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GORIO: GPU-Centered Remote I/O for Graph ANNS over NVMe-oF

Gen Zhang, Wenhao Gu 2026-07-07
GPU Search Data Design Cache Scheduling Workload

GORIO addresses the problem that graph-based approximate nearest neighbor search (ANNS) vector indexes often exceed GPU memory, and existing CPU-centered remote I/O over NVMe-oF is poorly matched to GPU graph traversal. The method keeps all query evolution, page-miss generation, and resume decisions on the GPU, using the CPU only as an NVMe-oF transport proxy, with a two-layer design for GPU-direct remote I/O and ANNS-specific scheduling. On a SIFT1M DiskANN-style workload over RDMA NVMe-oF, GORIO achieves 1.31× speedup over the state-of-the-art remote-I/O reference and 3.73× over the direct remote page-cache path. This matters because it provides a concrete GPU-centered remote I/O substrate that significantly accelerates graph ANNS for vector databases and retrieval-augmented generation services.

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Efficient Discovery of Conditional Dependencies with Desbordante

Ivan Kozhukov, Dmitry Fedoseev, Maksim Emelyanov, Artem Smola 2026-07-07
Data

The problem is the computationally demanding discovery of conditional functional dependencies (CFDs) from data. The method builds on the CFDFinder algorithm with algorithmic and engineering improvements, including parallelization, to produce ParCFDFinder integrated into the Desbordante data profiler. Experimental results show speedups of up to 318× (118× average) and memory reductions of up to 23× (14× average) compared to the Java-based Metanome implementation. This matters because it enables convenient CFD discovery on datasets with hundreds of thousands of rows on a commodity machine within reasonable time.

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SMART: A Machine Learning and Monte Carlo Framework for Rapid Analysis of Stochastic Transistor Aging and Process Variation in Digital Circuits

Arash Esshaghi, Siavash Es'haghi, Gholamreza Shahabadi, Alireza Moradi 2026-07-07
Design Simulation

The problem is that traditional reliability analysis for digital circuits under stochastic transistor aging and process variation is computationally prohibitive for large designs. SMART integrates machine learning with Monte Carlo simulation, using Random Forest regression and Bayesian optimization to predict gate delay distributions without costly parameter extraction. Experimental validation on ISCAS85 benchmarks shows a 94.54% reduction in analysis time with only 1.63% average accuracy error. This matters because it enables scalable, high-fidelity reliability analysis for designing resilient digital systems in advanced CMOS nodes.

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